Board Schematics

• Error Logger
• Fib Interpreter
• Front Panel
• J3 to Transition Module
• Master Clock
• Miscellaneous
• Pipeline Capacitor Emulator
• Readout State Machine
• Taxi Decoder
• VME Interface

FPGA Program Schematics

• Buffer Manager: Manages buffer
• Buffer Manager main schematic
• Error Logger: Tracks and logs SRC (VRB, FFO) errors
• Error Logger main schematic
• Run Modes state machine
• VME interface state machine
• Fatal Error Mask subroutine
• Fib Interpreter: Emulates Fib commands and controls G-Link connection to FFO's
• Fib Interpreter main schematic
• Fib Command Emulator Fifo controller state machine
• Controller for SRCTM GLink state machine
• VME interface state machine
• Master Clock: Syncronizes to or emulates CDF clock signals
• Master Clock main schematic
• Phase detector schematic
• Seven 19ns phases of 132ns state machine
• Pipeline Capacitor Emulator: Simulates the pipeline register of the chips
• Pipeline main schematic page 1 2
• 6 to 45 demultiplexer subroutine
• Tagged cell fifo subroutine
• Pipeline Latency Memory subroutine
• Pipeline write address overflow subroutine
• Skip logic subroutine
• Pipeline state storage subroutine
• Write Address subroutine
• Run Modes state machine
• VME interface state machine
• Readout State Machine: Controls the readout of the chips (main function of board)
• RSM main schematic pages 1, 2, 3, 4, 5, 6, 7, 8.
• Clear Errors state machine
• Halt Recover Run state machine
• Level 2 Accept state machine
• Back-end State state machine
• Readout state machine
• Preamp Reset state machine
• Run Modes state machine
• SRC Error: Too many L1A state machine
• SRC Error: L1A/L2A buffer conflicts state machine
• VME interface state machine
• Taxi Decoder: Decodes nine bit L1 and L2 words to commands
• Main schematic pages
• Halt Recover Run state machine
• TS Emulator: Emulates TS commands
• Main schematic pages
• L1A trigger delay subroutine
• Protocol Rules subroutine
• Automatic L2 mode state machine
• Emulated HRR state machine
• Emulator mode controller (main state machine)
• Two L1A state machine
• VME Interface state machine
• Send Forced L2A subroutine
• Syncronizer (Manual Mode) subroutine
• Wait for gap for L1A subroutine
• VME Interface: Decode VME addresses to the other chips
• Main schematic pages
• VME addresses state machine

FPGA MCS Files

• Buffer Manager:
• Version 4
• Error Logger:
• Version 8
• Fib Interpreter:
• Version 5
• Master Clock:
• Version 31
• Pipeline Capacitor Emulator:
• Version 9
• Readout State Machine:
• Version 5
• Version 6: removed abort readout and PRD2 without digitize
• Version 7: revert to Version 5 and add extra delay for setting of VRB scan busy flag
• Taxi Decoder:
• Version 16
• TS Emulator:
• Version 26
• VME Interface:
• Version 4

The XC4025 RSM attempt

The Two SRC attempt

• The rsm mcs file version 13

SRCTM:

• The SRCTM documentation .doc,
• The SRCTM schematic PDF, ps
.